The project is focused on advanced research and training in three key areas of microelectronics, promoting collaboration with industry and the internationalization of academic and research activities.
Photonic Area: Activities related to (1) training in Silicon Photonics with highly specialized short courses in integrated photonics; (2) two high impact research projects in integrated photonics, specifically in integrated photonic sensors and in optical systems for wireless communications.
Digital Area: Activities related to (1) training of PhD researchers and dissemination of results in scientific forums; (2) high impact research focused on two main areas: advanced microprocessors and alternative architectures. In particular: technologies to optimize performance, energy efficiency and hardware costs in heterogeneous embedded systems, including accelerators and reconfigurable architectures; design of intelligent applications in various domains adapted to heterogeneous embedded platforms; integration of techniques and technologies from different areas, covering hardware, software and simulation tools.
Analogical Area: Activities related to (1) supporting communication systems based on baseband processing; (2) developing integrated transceivers for next-generation communications applications; (3) collaborating with local and regional companies in quantum system design projects based on RF design technologies.

This project aims to provide an accessible and efficient solution for integrating FP units into the RISC-V architecture using the HUB format. The advantages of our proposal are multifaceted and firmly rooted in both technical and strategic considerations. First and foremost, the adoption of the HUB numerical representation format in our project offers a compelling advantage: the ability to significantly reduce the processor's area and power consumption, all while maintaining precision in calculations. This optimization addresses a critical concern in modern computing, where energy efficiency and compact design are paramount, particularly in portable devices and embedded systems. By achieving this reduction in resource utilization without sacrificing computational accuracy, our project aligns with the current industry trends and European initiatives aimed at sustainable and efficient computing solutions.

This project plans to provide architectural and processing solutions at different systems of the computing continuum for data-driven and data-intensive applications, with the objective of improving computing performance, energy efficiency and/or processing flexibility for such workloads. The research team is made up of groups that work in the field of computer architectures and accelerators, and efficient programming models and techniques targeting data-intensive and data-driven applications.

The objective of HiPEAC is to stimulate and reinforce the development of the dynamic European computing ecosystem that supports the digital transformation of Europe. It does so by guiding the future research and innovation of key digital, enabling, and emerging technologies, sectors, and value chains. The longer term goal is to strengthen European leadership in the global data economy and to accelerate and steer the digital and green transitions through human-centred technologies and innovations. This will be achieved via mobilising and connecting European partnerships and stakeholders to be involved in the research, innovation and development of computing and systems technologies. They will provide roadmaps supporting the creation of next-generation computing technologies, infrastructures, and service platforms.
The HiPEAC CSA proposal directly addresses the research, innovation, and development of next generation computing and systems technologies and applications. The overall goal is to support the European value chains and value networks in computing and systems technologies across the computing continuum from cloud to edge computing to the Internet of Things (IoT).

This project is located in the broad context of data-intensive computing on modern HPC systems based on heterogeneous architectures. We plan to provide solutions at different levels, architecture, system and application, to perform efficiently (regarding performance and energy) data-intensive processing. These solutions cover three main lines of research: architectures, programming models and techniques, and applications.

Cyber-physical systems combine physical devices with computational resources for control and communication. Embedded computing is key for computers to interact directly with the physical world. The most common cyber-physical systems are modern cars, in which computers control the engine, braking, vehicle stability and support the driver. Cyber-physical systems are also present in energy networks, factories, automated warehouses as well as aeroplanes or trains. The EU-funded HiPEAC project is a coordination and support action that aims to structure, connect and cross-fertilise the European academic and industrial research and innovation communities in embedded computing and cyber-physical systems. It will bring together all actors and stakeholders in the field of cyber-physical systems of systems (CPSoS).

The main objective of the project is to design NMC (Near Memory Computing) architectures based on 3D memory technologies to accelerate Big Data applications and reduce their energy consumption, especially those that exhibit low data access locality. Both enhancements will focus on reducing data traffic between the processor and memory by moving the sections of code that cause most of this traffic to specific processing units located close to where the data resides.

The main objective of the project is the design of an NDP (Near Data Processing) architecture that optimizes the performance of data intensive applications, both structured and unstructured, but especially the latter. The performance improvement will focus on minimizing data traffic in the “slow” processor-memory channel by shifting the processing that causes most of this traffic to the logic layer included in the 3D memory module, taking advantage of the “fast” TSV channels.

The interaction between High-Performance computing (HPC) and Artificial Intelligence (AI) is creating a new horizon, "High-Performance Artificial Intelligence" (HPAI), that is fueling the growth of platforms, applications and products empowered by AI. Although AI is not a new field of research, recent advances in HPC have given AI the necessary tools to become a game-changing technology. Enabled by supercomputing technologies, AI techniques are making AI algorithms practical for many new use cases, and drawing a significant amount of interest from the private sector.
The activities of the HPC4IA network have been designed with the purpose of: 1) promoting the dissemination of the knowledge and methodologies used throughout the Spanish community; 2) allowing close collaboration between the participating groups with the aim of optimizing and improving current applications; and 3) foster participation in HPC4IA initiatives in Europe, ensuring the position of research groups on the international scene.

The main objective of this project is the design of hardware/software technologies to improve the efficiency (performance-energy ratio) of modern HPC architectures when executing data-intensive applications. Although we are interested in any kind of data-intensive applications, we put special focus on a class of applications with low locality and low arithmetic intensity. These applications, which typically exhibit large potential parallelism, however hardly scale in current HPC architectures due to the saturation of the memory channels.

The project focuses on key aspects of logical long-term preservation of digital information. In particular, three classes of problems will be studied: physical (degradation of the physical environment and hardware obsolescence), software (obsolescence of software and encoding formats) and content (integrity and authenticity of archived data). The developments will be accomplished within a highly distributed scheme to favor scalability.

The main objective of this project is the design of solutions in different areas to improve the efficiency and programming of high performance computing (HPC) systems considering application domains in various fields of science and engineering. The project proposal is a natural continuation of previous research in the HPC field, from the architecture to applications, where the group has extensive knowledge of the involved technologies and their evolution.

The SyeC network activities have been designed with the purpose of 1) favoring the dissemination of the know-how and skills for general use by the community, 2) enabling close collaborations between groups from different scientific domains to either optimize current algorithms and applications or re-use findings and experiences across disciplines, and 3) fostering the participation of group leaders in international HPC and BigData co-design initiatives and consortia, securing the position of Spanish research groups in the international scene.

This project proposes a series of research lines interrelated and developed in the context of high-performance computing. The project is supported by previous research done by the group, and establishes new challenges that arise as a consequence of the rapid evolution of high-performance computing systems. In particular, our group participates in providing solutions to improve the performance of new homogeneous and heterogeneous systems at the execution model, compiler, runtime and microarchitecture levels.

This project proposes the study the currently dominant high-performance architectures, specially the new multi-core processors. In particular, our group participates in the analysis and automatic exploitation of parallelism and locality for applications based on complex data structures (pointers, indirections ...), as well as in microarchitectural support for those applications.

The main aim of this project is offering a national framework for research groups expert in supercomputing applications to collaborate together with expert hardware/software machine designers in order to design and use these machines efficiently in the near future. Our participation is based in our expertise in the analysis and automatic optimization of real-life applications.

The aim of this project is tackling some of the problems that current implementations of transactional memory systems suffer, with an important impact in their performance. Specifically, we proposes to provide solutions to the design of signatures for improving the efficiency of conflict detection, and to extend the model to heterogeneous architectures.