Conference/Workshop Papers
Author: J. Hormigo

2024

2023

High-Throughput DTW Accelerator with Minimum Area in AMD FPGA by HLS [doi]
M. Hormigo-Jimenez, J. Hormigo
38th Conference on Design of Circuits and Integrated Systems (DCIS'23), Malaga (Spain), November 2023

2022

2021

Introduce Metodologías Activas en tu Clase, Indispensable en Tiempos de Pandemia [link]
E. Hendrix, F.M. Castro, D.A. Constantinescu, F. Corbera, S. Gonzalez-Navarro, M. Gonzalez, J. Hormigo, J.R. Cozar, A. Rodriguez
XXXI Jornadas de Paralelismo (JP'20/21) (parte de las Jornadas Sarteco), Malaga (Spain), September 2021

FPGA Acceleration of Bit-True Simulations for Word-Length Optimization [doi]
J. Hormigo, G. Caffarena
IEEE 28th Symposium on Computer Arithmetic (ARITH'21), Lyngby, Denmark, June 2021

2020

Floating-Point Fused Multiply-Add under HUB Format [doi]
J. Hormigo, J. Villalba, S. Gonzalez-Navarro
IEEE 27th Symposium on Computer Arithmetic (ARITH'20), Portland (OR, USA), June 2020

2019

Reproducible Summation Under HUB Format [doi]
J. Villalba, J. Hormigo, F. Jaime
IEEE 26th Symposium on Computer Arithmetic (ARITH'19), Kyoto (Japan), June 2019

2018

Project Based Learning on Industrial Informatics: Applying IoT to Urban Garden [doi]
J. Hormigo, A. Rodriguez
XIII Technologies Applied to Electronics Teaching Conference (TAEE'18), La Laguna (Spain), June 2018

2017

Floating Point Square Root under HUB Format [doi]
J. Villalba, J. Hormigo
IEEE International Conference on Computer Design (ICCD’2017), Boston (MA), USA, November 2017

Normalizing or Not Normalizing? An Open Question for Floating-Point Arithmetic in Embedded Systems [doi]
S. Gonzalez-Navarro, J. Hormigo
IEEE 24th Symposium on Computer Arithmetic (ARITH’17), London (UK), July 2017

2016

2015

Improving Fixed-Point Implementation of QR Decomposition by Rounding-to-Nearest [doi]
S.D. Muñoz, J. Hormigo
19th IEEE International Symposium on Consumer Electronics (ISCE’15), Madrid (Spain), June 2015

Simplified Floating-Point Units for High Dynamic Range Image and Video Systems [doi]
J. Hormigo, J. Villalba
19th IEEE International Symposium on Consumer Electronics (ISCE’15), Madrid (Spain), June 2015

2014

Optimizing DSP Circuits by a New Family of Arithmetic Operators [doi]
J. Hormigo, J. Villalba
48th Asilomar Conference on Signals, Systems and Computers, Pacific Grove (CA, USA), November 2014

2013

Efficient Floating-Point Representation for Balanced Codes for FPGA Devices [doi]
J. Villalba, J. Hormigo, F. Corbera, M. Gonzalez, E.L. Zapata
IEEE 31st International Conference on Computer Design (ICCD'13), Asheville (NC), USA, October 2013 (Best Paper Award)

2012

FGPA Implementation of QR Decomposition for Medium Size Matrices
S.D. Muñoz, J. Hormigo, E.L. Zapata
XXVII Conference on Design of Circuits and Integrated Systems (DCIS'12), Avignon (France), November 2012

Acelerador Hardware de Bajo Coste para Bus PCI Convencional [link]
F. Quiles, M.A. Montijano, C.C. Moreno, M.Brox, M. Ortiz, J. Hormigo, J. Villalba
Annual Seminar on Automation, Industrial Electronics and Instrumentation (SAAEI’12), Guimaraes (Portugal), July 2012

2011

Convolution Computation in FPGA Based on Carry-Save Adders and Circular Buffers [doi]
C.D. Moreno, M.P. Martinez, F.J. Bellido, J. Hormigo, M.A. Ortiz, F.J. Quiles
3rd International ICST Conference on IT Revolutions (ICST’11), Cordoba (Spain), March 2011

2010

UCORE: Reconfigurable Platform for Educational Purposes [doi]
F. Quiles, M. Ortiz, J. Hormigo, J. Villalba
International Conference on ReConFigurable Computing and FPGAs, Cancun (Mexico), December 2010

2009

Efficient Mapping on FPGA of Convolution Computation Based on Combined CSA-CPA Accumulator [doi]
C.D. Moreno, F. Quiles, M. Ortiz, M. Brox, J. Hormigo, J. Villalba, E.L. Zapata
16th IEEE International Conference on Electronics, Circuits and Systems (ICECS'09), Yasmine Hammamet, Tunisia, December 2009

Efficient Implementation of Carry-Save Adders in FPGAs [doi]
J. Hormigo, M. Ortiz, F. Quiles, F.J. Jaime, J. Villalba, E.L. Zapata
20th IEEE International Conference on Applicaction Specific Systems, Architectures and Processors (ASAP'09), Boston (MA), USA, July 2009

2008

New SIMD Instructions set for Image Processing Applications Enhacement [doi]
F.J. Jaime, J. Hormigo, J. Villalba, E.L. Zapata
15th IEEE International Conference on Image Processing (ICIP'08), San Diego (CA), USA, October 2008

SIMD Enhacements for a Hough Transform Implementation [doi]
F.J. Jaime, J. Hormigo, J. Villalba, E.L. Zapata
11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD'08), Parma (Italy), September 2008

Decimal Left Shifters for Binary Numbers
J. Hormigo, S. Gonzalez-Navarro, M. Schulte
8th Conference on Real Numbers and Computers (RNC8), Santiago de Compostela, Spain, July 2008

2007

Profit Analysis of Instructions with Parallel Access to Memory
F.J. Jaime, J. Villalba, J. Hormigo, E.L. Zapata
Workshop on Application Specific Processors (WASP 2007), Salzburg, Austria, October 2007

Improving the Troughput of On-line Addition for Data Streams [doi]
J. Villalba, J. Hormigo, T. Lang
18th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP’07), Montreal, Canada, July 2007

Hardware Accelerators for the Microblaze Software Embedded Processor [link]
M. Hernandez-Calviño, J.I. Benavides, S.R. Geninatti, J. Hormigo, J. Villalba
III Southern Conference on Programmable Logic (SPL2007), Mar del Plata, Argentina, February 2007 (poster)

2006

Pipelined Range Reduction for Floating Point Numbers [doi]
F.J. Jaime, J. Villalba, J. Hormigo, E.L. Zapata
17th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'06), Steamboat Springs (CO, USA), September 2006

Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA [doi]
J. Olivares, J.I. Benavides, J. Hormigo, J. Villalba, E.L. Zapata
16th International Conference on Field Programmable Logic and Applications (FPL'06), Madrid (Spain), August 2006

Pipelined Architecture for Accurate Floating Point Range Reduction [link]
F.J. Jaime, J. Villalba, J. Hormigo, E.L. Zapata
7th Conference on Real Numbers and Computers (RNC'06), Loria (Nancy, France), July 2006

2005

On-line Multioperand Addition Based on On-line Full-Adders [doi]
J. Villalba, J. Hormigo, J.M. Prades, E.L. Zapata
16th IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP’05), Samos (Greece), July 2005

Hardware Implementation of the Wavelet Transform for JPEG2000 [doi]
J. Hormigo, J.M. Prades, J. Villalba, E.L. Zapata
SPIE Symposium on Microtechnologies for the New Millennium, Sevilla (Spain), May 2005
(Proc. SPIE 5837, VLSI Circuits and Systems II, J.F. Lopez, F.V. Fernandez, J.M. Lopez-Villegas and J.M. dela Rosa, Eds.)

2004

Optimized FPGA Implementation of Trigonometric Functions with Large Input Arguments
J. Hormigo, M. Sanchez, M. Gonzalez, G. Bandera, J. Villalba
XIX Conference on Design of Circuits and Integrated Systems (DCIS'04), Bordeaux (France), November 2004

Alternativas al Cálculo de la Estimación de Movimiento en MPEG
J.I. Benavides, J. Hormigo, J. Olivares, J. Villalba
XV Jornadas de Paralelismo (JJPP'04), Almeria (Spain), September 2004

Minimum Sum of Absolute Differences Implementation in a Single FPGA Device [doi]
J. Olivares, J. Hormigo, J. Villalba, I. Benavides
14th International Conference on Field Programmable Logic and Applications (FPL'04),, Leuven (Belgium), August-September 2004
(Springer, LNCS 3203, J. Becker, M. Platzner and S. Vernalde, Eds., pp. 986-990)

Estimación de Movimiento en MPEG Mediante Técnicas de Aritmética On-Line Sobre FPGA
J. Hormigo, J. Olivares, I. Benavides, J. Villalba
3ra Conferencia Iberoamericana en sistemas, Cibernética e Informática (CISCI'04), Orlando (FL, USA), July 2004

New On-Line Comparator with No On-Line Delay
J. Hormigo, J. Olivares, J. Villalba, I. Benavides
8th World Muticonference on Systemics, Cybernetics and Informatics (SCI2004), Orlando (FL, USA), July 2004

Evaluation of Elementary Functions Using Multimedia Features [doi]
G. Bandera, M. Gonzalez, J. Villaba, J. Hormigo, E.L. Zapata
18th International Parallel and Distributed Processing Symposium (IPDPS'04), Santa Fe (NM, USA), April 2004

2003

Implementación de un Sumador Matricial en FPGA Mediante Técnicas de Aritmrética On-Line Radix-2 SD
J. Olivares, J.I. Benavides, J. Villalba, J. Hormigo
XIV Jornadas de Paralelismo (JJPP'03), Leganes, Madrid (Spain), September 2003

Texture Segmentation and a Analysis Using Local Spectral Methods [doi]
G. Cristobal, S. Fischer, M. Forero-Vargas, R. Redondo, J. Hormigo
7th International Symposium on Signal Processing and its Applications (ISSPA'03), Paris (France), July 2003

2002

Polynomial Evaluation on Multimedia Processor [doi]
J. Villalba, G. Bandera, M. Gonzalez, J. Hormigo, E.L. Zapata
13th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'02), San Jose (CA, USA), July 2002, pp. 265-277

2001

Bit Stream Processor for Object Based MPEG-4 Profiles [doi]
K.A. Jacob, J. Hormigo
35th Asilomar Conference on Signals, Systems and Computers, Pacific Grove (CA, USA), November 2001

2000

MMX-like Architecture Extension to Support the Rotation Operation [doi]
J. Villalba, J. Hormigo, M. Gonzalez, E.L. Zapata
IEEE International Conference on Multimedia and Expo (ICME'00), New York (NY, USA), July-August 2000

1999

FPGA Implementation of a CORDIC Processor with Reduced Number of Iterations
M. Gonzalez, J. Hormigo, J. Villalba, E. Saez, E.L. Zapata
14th Conference on Design of Circuits and Integrated Systems (DCIS'99), Palma de Mallorca (Spain), November 1999

Arithmetic Unit for the Computation of Interval Elementary Functions [doi]
J. Hormigo, J. Villalba, E.L. Zapata
25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millenium, Milan (Italy), September 1999

Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm [doi]
J. Hormigo, J. Villalba, E.L. Zapata
14th IEEE Symposium on Computer Arithmetic (ARITH-14), Adelaide (Australia), April 1999

1998

FPGA Implementation of a Variable Precision CORDIC Processor
E. Saez, J. Villalba, J. Hormigo, F.J. Quiles, J.I. Benavides, E.L. Zapata
13th Conference on Design of Circuits and Integrated Systems (DCIS'98), Madrid (Spain), November 1998

CORDIC Algorithm with Digits Skipping [doi]
J. Hormigo, J. Villalba, E.L. Zapata
32th Asilomar Conference on Signals, Systems and Computers, Pacific Grove (CA, USA), November 1998

A Hardware Approximation to Interval Arithmetic for Sine and Cosine Functions [doi]
J. Hormigo, J. Villalba, E.L. Zapata
IMACS/GAMS International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics (SCAN'98), Szeged (Hungary), September 1998
(Springer, Developments on Reliable Computing, T. Csendes, Ed., pp. 31-41)

1997

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