Journal Papers
Author: J. Villalba

2024

2023

2022

High-Radix Formats for Enhancing Floating-Point FPGA Implementations [doi]
J. Villalba, J. Hormigo
Circuits, Systems, and Signal Processing, 41, March 2022, pp. 1683-1703

2021

2020

2019

Fast HUB Floating-Point Adder for FPGA [doi]
J. Villalba, J. Hormigo, S. Gonzalez-Navarro
IEEE Transactions on Circuits and Systems II: Express Briefs, 66 (6), June 2019, pp. 1028-1032

2018

Unbiased Rounding for HUB Floating-Point Addition [doi]
J. Villalba, J. Hormigo, S. Gonzalez-Navarro
IEEE Transactions on Computers, 67 (9), September 2018, pp. 1359-1365

2017

Introduction to the Special Issue on Computer Arithmetic [doi]
J. Hormigo, J. Muller, S. Oberman, N. Revol, A. Tisserand, J. Villalba
IEEE Transactions on Computers, 66 (12), December 2017, pp. 1991-1993

HUB Floating Point for Improving FPGA Implementations of DSP Applications [doi]
J. Hormigo, J. Villalba
IEEE Transactions on Circuits and Systems II: Express Briefs, 64 (3), March 2017, pp. 319-323

2016

Decimal Multiformat Online Addition [doi]
C. Garcia, S. Gonzalez-Navarro, P. Balboa, J. Villalba
IEEE Transactions on Computers, 65 (10), October 2016, 3203-3209

New Formats for Computing with Real-Numbers under Round-to-Nearest [doi]
J. Hormigo, J. Villalba
IEEE Transactions on Computers, 65 (7), July 2016, pp. 2158-2168

Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest [doi]
J. Hormigo, J. Villalba
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24 (6), June 2016, pp. 2369-2377

2015

2014

2013

Multioperand Redundant Adders on FPGAs [doi]
J. Hormigo, J. Villalba, E.L. Zapata
IEEE Transactions on Computers, 62 (10), October 2013, pp. 2013-2025

2012

Redundant Floating Point Decimal CORDIC Algorithm [doi]
A. Vazquez, J. Villalba, E. Antelo, E.L. Zapata
IEEE Transactions on Computers, 61 (11), November 2012, pp. 1551-1562

Radix-2 Multioperand and Multiformat Streaming Online Addition [doi]
J. Villalba, T. Lang, J. Hormigo
IEEE Transactions on Computers, 61 (6), June 2012, pp. 790-803

2011

High-Speed Algorithms and Architectures for Range Reduction Computation [doi]
F.J. Jaime, M.A. Sanchez, J. Hormigo, J. Villalba, E.L. Zapata
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19 (3), March 2011, pp. 512-516

2010

Enhanced Scaling-Free CORDIC [doi]
F.J. Jaime, M.A. Sanchez, J. Hormigo, J. Villalba, E.L. Zapata
IEEE Transactions on Circuits and Systems I, 57 (7), July 2010, pp. 1654-1662

2009

2008

Pipelined Architecture for Additive Range Reduction [doi]
F.J. Jaime, J. Villalba, J. Hormigo, E.L. Zapata
Journal of Signal Processing Systems, 53 (1-2), November 2008, pp. 103-112

A Low-Latency Pipelined 2D and 3D CORDIC Processors [doi]
E. Antelo, J. Villalba, E.L. Zapata
IEEE Transactions on Computers, 57 (3), March 2008, pp. 404-417

2007

2006

SAD Computation based on On-line Arithmetic for Motion Estimation [doi]
J. Olivares, J. Hormigo, J. Villalba, J.I. Benavides, E.L. Zapata
Microprocessors and Microsystems, 30 (5), August 2006, pp. 250-258

Double-Residue Modular Range Reduction for Floating-Point Hardware Implementations [doi]
J. Villalba, T. Lang, M. Gonzalez
IEEE Transactions on computers, 55 (3), March 2006, pp. 254-267

2005

2004

Estimación de Movimiento en MPEG mediante Técnicas de Aritmética On-Line sobre FPGA [link]
J. Olivares, J. Hormigo, J.I. Benavides, J. Villalba, E.L. Zapata
Revista Iberoamericana de Sistemas, Cibernética e Informática, 1 (2), 2004, pp. 36-41

CORDIC Processor for Variable-Precision Interval Arithmetic [doi]
J. Hormigo, J. Villalba, E.L. Zapata
Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 37 (1), May 2004, pp. 21-39

2003

2002

2001

2000

1999

1998

Parallel Compensation of Scale Factor for the CORDIC Algorithm [doi]
J. Villalba, T. Lang, E.L. Zapata
Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 19 (3), August 1998, pp. 227-241

Radix-4 Vectoring CORDIC Algorithm and Architectures [doi]
J. Villalba, E.L. Zapata, E. Antelo, J.D. Bruguera
Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 19 (2), July 1998, pp. 127-147

1997

High Performance Rotation Architectures Based on Radix-4 CORDIC Algorithm [doi]
E. Antelo, J. Villalba, J.D. Bruguera, E.L. Zapata
IEEE Transactions on Computers, 46 (8), August 1997, pp. 855-870

1996

CORDIC Based Parallel/Pipelined Architecture for the Hough Transform [doi]
J.D. Bruguera, N. Guil, T. Lang, J. Villalba, E.L. Zapata
Journal of VLSI Signal Processing for Signal, Image and Video Technology, 12, June 1996, pp. 207-221

1995

A Fast Hough Transform for Segment Detection [doi]
N. Guil, J. Villalba, E.L. Zapata
IEEE Transactions on Image Processing, 4 (11), November 1995, pp. 1541-1548

1994

1993

1992

1991

1990

1989

1988

1986

1985

1984

1983

1982

1981