All Papers
Author: J. Villalba

2024

Floating Point HUB Adder for RISC-V Sargantana Processor [arXiv]
G. Bandera, J. Salamero, M. Moreto, J. Villalba
arXiv:2401.09464v1 [cs.AR], January 2024

2023

2022

High-Radix Formats for Enhancing Floating-Point FPGA Implementations [doi]
J. Villalba, J. Hormigo
Circuits, Systems, and Signal Processing, 41, March 2022, pp. 1683-1703

2021

2020

Floating-Point Fused Multiply-Add under HUB Format [doi]
J. Hormigo, J. Villalba, S. Gonzalez-Navarro
IEEE 27th Symposium on Computer Arithmetic (ARITH'20), Portland (OR, USA), June 2020

2019

Fast HUB Floating-Point Adder for FPGA [doi]
J. Villalba, J. Hormigo, S. Gonzalez-Navarro
IEEE Transactions on Circuits and Systems II: Express Briefs, 66 (6), June 2019, pp. 1028-1032

Reproducible Summation Under HUB Format [doi]
J. Villalba, J. Hormigo, F. Jaime
IEEE 26th Symposium on Computer Arithmetic (ARITH'19), Kyoto (Japan), June 2019

2018

Unbiased Rounding for HUB Floating-Point Addition [doi]
J. Villalba, J. Hormigo, S. Gonzalez-Navarro
IEEE Transactions on Computers, 67 (9), September 2018, pp. 1359-1365

2017

Introduction to the Special Issue on Computer Arithmetic [doi]
J. Hormigo, J. Muller, S. Oberman, N. Revol, A. Tisserand, J. Villalba
IEEE Transactions on Computers, 66 (12), December 2017, pp. 1991-1993

Floating Point Square Root under HUB Format [doi]
J. Villalba, J. Hormigo
IEEE International Conference on Computer Design (ICCD’2017), Boston (MA), USA, November 2017

Motivando al Alumno de Ingeniería Mediante la Plataforma Raspberry Pi [link]
R. Asenjo, S. Gonzalez-Navarro, F. Corbera, A. Navarro, A. Rodriguez, J. Villalba, E.M.T. Hendrix
XXVIII Jornadas de Paralelismo (JJPP'17) (parte de las Jornadas Sarteco), Malaga (Spain), September 2017

HUB Floating Point for Improving FPGA Implementations of DSP Applications [doi]
J. Hormigo, J. Villalba
IEEE Transactions on Circuits and Systems II: Express Briefs, 64 (3), March 2017, pp. 319-323

2016

Decimal Multiformat Online Addition [doi]
C. Garcia, S. Gonzalez-Navarro, P. Balboa, J. Villalba
IEEE Transactions on Computers, 65 (10), October 2016, 3203-3209

Digit Recurrence Floating-Point Division under HUB Format [doi]
J. Villalba
23nd IEEE Symposium on Computer Arithmetic (ARITH’16), Santa Clara (CA), USA, July 2016

New Formats for Computing with Real-Numbers under Round-to-Nearest [doi]
J. Hormigo, J. Villalba
IEEE Transactions on Computers, 65 (7), July 2016, pp. 2158-2168

Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest [doi]
J. Hormigo, J. Villalba
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24 (6), June 2016, pp. 2369-2377

2015

Simplified Floating-Point Units for High Dynamic Range Image and Video Systems [doi]
J. Hormigo, J. Villalba
19th IEEE International Symposium on Consumer Electronics (ISCE’15), Madrid (Spain), June 2015

2014

Optimizing DSP Circuits by a New Family of Arithmetic Operators [doi]
J. Hormigo, J. Villalba
48th Asilomar Conference on Signals, Systems and Computers, Pacific Grove (CA, USA), November 2014

2013

Multioperand Redundant Adders on FPGAs [doi]
J. Hormigo, J. Villalba, E.L. Zapata
IEEE Transactions on Computers, 62 (10), October 2013, pp. 2013-2025

Efficient Floating-Point Representation for Balanced Codes for FPGA Devices [doi]
J. Villalba, J. Hormigo, F. Corbera, M. Gonzalez, E.L. Zapata
IEEE 31st International Conference on Computer Design (ICCD'13), Asheville (NC), USA, October 2013 (Best Paper Award)

2012

Redundant Floating Point Decimal CORDIC Algorithm [doi]
A. Vazquez, J. Villalba, E. Antelo, E.L. Zapata
IEEE Transactions on Computers, 61 (11), November 2012, pp. 1551-1562

Decimal On-line Multioperand Addition [link]
C. Vega, S. Gonzalez-Navarro, J. Villalba, E.L. Zapata
47th Asilomar Conference on Signals, Systems and Computers, Asilomar (CA), USA, November 2012

Pixel-based BAckground Initialization Using Spatio-Temporal Restrictions [doi]
J. Villalba, J.M. Gonzalez-Linares, J.R. Cozar, N. Guil
16th International Conference on Knowledge-Based and Intelligent Information & Engineering Systems (KES'12), San Sebastian (Spain), September 2012
(Advances in Knowledge-Based and Intelligent Information and Engineering Systems, Volume 243: Frontiers in Artificial Intelligence and Applications, IOS Press, pp. 1703-1711, 2012)

On-line Decimal Adder with RBCD Representation [doi]
C. Vega, S. Gonzalez-Navarro, J. Villalba, E.L. Zapata
23th IEEE International Conference on Application Specific Systems, Architectures and Processors (ASAP'12), Delft (The Netherlands), July 2012

Acelerador Hardware de Bajo Coste para Bus PCI Convencional [link]
F. Quiles, M.A. Montijano, C.C. Moreno, M.Brox, M. Ortiz, J. Hormigo, J. Villalba
Annual Seminar on Automation, Industrial Electronics and Instrumentation (SAAEI’12), Guimaraes (Portugal), July 2012

Radix-2 Multioperand and Multiformat Streaming Online Addition [doi]
J. Villalba, T. Lang, J. Hormigo
IEEE Transactions on Computers, 61 (6), June 2012, pp. 790-803

2011

Conversion between DPD and RBCD for On-Line Arithmetic Computation
S. Gonzalez-Navarro, C. Garcia, J. Villalba
XXII Jornadas de Paralelismo (JJPP’11), La Laguna, Tenerife (Spain), September 2011

Kernel-Based Object Tracking Using a Simple Fuzzy Color Histogram [doi]
J. Villalba, J.M. Gonzalez-Linares, J.R. Cozar, N. Guil
International Work Conference on Artificial Neural Networks (IWANN’11), Torremolinos-Malaga (Spain), June 2011
(Springer, LNCS 6691, J. Cabestany, I. Rojas and G. Joya, Eds., pp. 513-519)

High-Speed Algorithms and Architectures for Range Reduction Computation [doi]
F.J. Jaime, M.A. Sanchez, J. Hormigo, J. Villalba, E.L. Zapata
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19 (3), March 2011, pp. 512-516

2010

UCORE: Reconfigurable Platform for Educational Purposes [doi]
F. Quiles, M. Ortiz, J. Hormigo, J. Villalba
International Conference on ReConFigurable Computing and FPGAs, Cancun (Mexico), December 2010

Enhanced Scaling-Free CORDIC [doi]
F.J. Jaime, M.A. Sanchez, J. Hormigo, J. Villalba, E.L. Zapata
IEEE Transactions on Circuits and Systems I, 57 (7), July 2010, pp. 1654-1662

2009

Efficient Mapping on FPGA of Convolution Computation Based on Combined CSA-CPA Accumulator [doi]
C.D. Moreno, F. Quiles, M. Ortiz, M. Brox, J. Hormigo, J. Villalba, E.L. Zapata
16th IEEE International Conference on Electronics, Circuits and Systems (ICECS'09), Yasmine Hammamet, Tunisia, December 2009

Efficient Implementation of Carry-Save Adders in FPGAs [doi]
J. Hormigo, M. Ortiz, F. Quiles, F.J. Jaime, J. Villalba, E.L. Zapata
20th IEEE International Conference on Applicaction Specific Systems, Architectures and Processors (ASAP'09), Boston (MA), USA, July 2009

Computation of Decimal Transcendental Functions using the CORDIC Algorithm [doi]
A. Vazquez, J. Villalba, E. Antelo
19th IEEE Symposium on Computer Arithmetic (ARITH'19), Portland (OR), USA, June 2009

2008

Pipelined Architecture for Additive Range Reduction [doi]
F.J. Jaime, J. Villalba, J. Hormigo, E.L. Zapata
Journal of Signal Processing Systems, 53 (1-2), November 2008, pp. 103-112

New SIMD Instructions set for Image Processing Applications Enhacement [doi]
F.J. Jaime, J. Hormigo, J. Villalba, E.L. Zapata
15th IEEE International Conference on Image Processing (ICIP'08), San Diego (CA), USA, October 2008

SIMD Enhacements for a Hough Transform Implementation [doi]
F.J. Jaime, J. Hormigo, J. Villalba, E.L. Zapata
11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD'08), Parma (Italy), September 2008

A Low-Latency Pipelined 2D and 3D CORDIC Processors [doi]
E. Antelo, J. Villalba, E.L. Zapata
IEEE Transactions on Computers, 57 (3), March 2008, pp. 404-417

2007

Profit Analysis of Instructions with Parallel Access to Memory
F.J. Jaime, J. Villalba, J. Hormigo, E.L. Zapata
Workshop on Application Specific Processors (WASP 2007), Salzburg, Austria, October 2007

Improving the Troughput of On-line Addition for Data Streams [doi]
J. Villalba, J. Hormigo, T. Lang
18th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP’07), Montreal, Canada, July 2007

Hardware Accelerators for the Microblaze Software Embedded Processor [link]
M. Hernandez-Calviño, J.I. Benavides, S.R. Geninatti, J. Hormigo, J. Villalba
III Southern Conference on Programmable Logic (SPL2007), Mar del Plata, Argentina, February 2007 (poster)

2006

Pipelined Range Reduction for Floating Point Numbers [doi]
F.J. Jaime, J. Villalba, J. Hormigo, E.L. Zapata
17th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'06), Steamboat Springs (CO, USA), September 2006

Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA [doi]
J. Olivares, J.I. Benavides, J. Hormigo, J. Villalba, E.L. Zapata
16th International Conference on Field Programmable Logic and Applications (FPL'06), Madrid (Spain), August 2006

SAD Computation based on On-line Arithmetic for Motion Estimation [doi]
J. Olivares, J. Hormigo, J. Villalba, J.I. Benavides, E.L. Zapata
Microprocessors and Microsystems, 30 (5), August 2006, pp. 250-258

Pipelined Architecture for Accurate Floating Point Range Reduction [link]
F.J. Jaime, J. Villalba, J. Hormigo, E.L. Zapata
7th Conference on Real Numbers and Computers (RNC'06), Loria (Nancy, France), July 2006

Double-Residue Modular Range Reduction for Floating-Point Hardware Implementations [doi]
J. Villalba, T. Lang, M. Gonzalez
IEEE Transactions on computers, 55 (3), March 2006, pp. 254-267

2005

Hardware para Intervalos
J. Hormigo, E.L. Zapata, J. Villalba
El Análisis de Intervalos en España: Desarrollos, Herramientas y Aplicaciones, Documenta Universitaria, 2005, pp. 87-95

Hybrid Residue Generators Using Carry-Save Adders
F.J. Jaime, J. Villalba, M. Gonzalez, E.L. Zapata
20th Conference on Design of Circuits and Integrated Systems (DCIS’05), Lisbon (Portugal), November 2005

On-line Multioperand Addition Based on On-line Full-Adders [doi]
J. Villalba, J. Hormigo, J.M. Prades, E.L. Zapata
16th IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP’05), Samos (Greece), July 2005

Low Latency Pipelined Circular CORDIC [doi]
E. Antelo, J. Villalba
17th IEEE Symposium on Computer Arithmetic (ARITH'05), Cape Cod (MA, USA), June 2005

Hardware Implementation of the Wavelet Transform for JPEG2000 [doi]
J. Hormigo, J.M. Prades, J. Villalba, E.L. Zapata
SPIE Symposium on Microtechnologies for the New Millennium, Sevilla (Spain), May 2005
(Proc. SPIE 5837, VLSI Circuits and Systems II, J.F. Lopez, F.V. Fernandez, J.M. Lopez-Villegas and J.M. dela Rosa, Eds.)

2004

Estimación de Movimiento en MPEG mediante Técnicas de Aritmética On-Line sobre FPGA [link]
J. Olivares, J. Hormigo, J.I. Benavides, J. Villalba, E.L. Zapata
Revista Iberoamericana de Sistemas, Cibernética e Informática, 1 (2), 2004, pp. 36-41

Optimized FPGA Implementation of Trigonometric Functions with Large Input Arguments
J. Hormigo, M. Sanchez, M. Gonzalez, G. Bandera, J. Villalba
XIX Conference on Design of Circuits and Integrated Systems (DCIS'04), Bordeaux (France), November 2004

Alternativas al Cálculo de la Estimación de Movimiento en MPEG
J.I. Benavides, J. Hormigo, J. Olivares, J. Villalba
XV Jornadas de Paralelismo (JJPP'04), Almeria (Spain), September 2004

Minimum Sum of Absolute Differences Implementation in a Single FPGA Device [doi]
J. Olivares, J. Hormigo, J. Villalba, I. Benavides
14th International Conference on Field Programmable Logic and Applications (FPL'04),, Leuven (Belgium), August-September 2004
(Springer, LNCS 3203, J. Becker, M. Platzner and S. Vernalde, Eds., pp. 986-990)

Estimación de Movimiento en MPEG Mediante Técnicas de Aritmética On-Line Sobre FPGA
J. Hormigo, J. Olivares, I. Benavides, J. Villalba
3ra Conferencia Iberoamericana en sistemas, Cibernética e Informática (CISCI'04), Orlando (FL, USA), July 2004

New On-Line Comparator with No On-Line Delay
J. Hormigo, J. Olivares, J. Villalba, I. Benavides
8th World Muticonference on Systemics, Cybernetics and Informatics (SCI2004), Orlando (FL, USA), July 2004

CORDIC Processor for Variable-Precision Interval Arithmetic [doi]
J. Hormigo, J. Villalba, E.L. Zapata
Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 37 (1), May 2004, pp. 21-39

2003

Implementación de un Sumador Matricial en FPGA Mediante Técnicas de Aritmrética On-Line Radix-2 SD
J. Olivares, J.I. Benavides, J. Villalba, J. Hormigo
XIV Jornadas de Paralelismo (JJPP'03), Leganes, Madrid (Spain), September 2003

2002

Polynomial Evaluation on Multimedia Processor [doi]
J. Villalba, G. Bandera, M. Gonzalez, J. Hormigo, E.L. Zapata
13th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'02), San Jose (CA, USA), July 2002, pp. 265-277

2001

Variable-Precision Exponential Evaluation [doi]
J. Hormigo, J. Villalba, M.J. Schulte
Scientific Computing, Validated Numerics, Interval Methods
(Springer, W. Kraemer and J.W. von Gudenberg, Eds., pp. 19-28, 2001)

2000

MMX-like Architecture Extension to Support the Rotation Operation [doi]
J. Villalba, J. Hormigo, M. Gonzalez, E.L. Zapata
IEEE International Conference on Multimedia and Expo (ICME'00), New York (NY, USA), July-August 2000

Hardware Algorithm for Variable-Precision Division
J. Hormigo , J. Villalba, M.J. Schulte
4th Conference on Real Numbers and Computers (RNC4), Dagstuhl (Saarland, Germany), April 2000

1999

FPGA Implementation of a CORDIC Processor with Reduced Number of Iterations
M. Gonzalez, J. Hormigo, J. Villalba, E. Saez, E.L. Zapata
14th Conference on Design of Circuits and Integrated Systems (DCIS'99), Palma de Mallorca (Spain), November 1999

Arithmetic Unit for the Computation of Interval Elementary Functions [doi]
J. Hormigo, J. Villalba, E.L. Zapata
25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millenium, Milan (Italy), September 1999

Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm [doi]
J. Hormigo, J. Villalba, E.L. Zapata
14th IEEE Symposium on Computer Arithmetic (ARITH-14), Adelaide (Australia), April 1999

Book Chapter: A Hardware Approach to Interval Artihmetic for Sine and Cosine Functions [doi]
J. Hormigo, J. Villalba, E.L. Zapata
Developments in Reliable Computing, (Springer, Dordrecht, T. Csendes Ed., pp. 31-41, 1999)

1998

FPGA Implementation of a Variable Precision CORDIC Processor
E. Saez, J. Villalba, J. Hormigo, F.J. Quiles, J.I. Benavides, E.L. Zapata
13th Conference on Design of Circuits and Integrated Systems (DCIS'98), Madrid (Spain), November 1998

CORDIC Algorithm with Digits Skipping [doi]
J. Hormigo, J. Villalba, E.L. Zapata
32th Asilomar Conference on Signals, Systems and Computers, Pacific Grove (CA, USA), November 1998

A Hardware Approximation to Interval Arithmetic for Sine and Cosine Functions [doi]
J. Hormigo, J. Villalba, E.L. Zapata
IMACS/GAMS International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics (SCAN'98), Szeged (Hungary), September 1998
(Springer, Developments on Reliable Computing, T. Csendes, Ed., pp. 31-41)

Multimedia Applications Based on Rotations
J. Villalba
Seminar No. 98351 on Architectural and Arithmetic Support for Multimedia, Dagstuhl (Saarland, Germany), August-September 1998

Parallel Compensation of Scale Factor for the CORDIC Algorithm [doi]
J. Villalba, T. Lang, E.L. Zapata
Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 19 (3), August 1998, pp. 227-241

Radix-4 Vectoring CORDIC Algorithm and Architectures [doi]
J. Villalba, E.L. Zapata, E. Antelo, J.D. Bruguera
Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 19 (2), July 1998, pp. 127-147

1997

Three-Dimensional Rotations Based on General Purpose 3D CORDIC Algorithm
D. Reche, J. Villalba, E.L. Zapata
XII International Conference on Design of Circuits and Integrated Systems (DCIS'97), Sevilla (Spain), November 1997

High Performance Rotation Architectures Based on Radix-4 CORDIC Algorithm [doi]
E. Antelo, J. Villalba, J.D. Bruguera, E.L. Zapata
IEEE Transactions on Computers, 46 (8), August 1997, pp. 855-870

Low Latency Word Serial CORDIC [doi]
J. Villalba, T. Lang
IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97), Zurich (Switzerland), July 1997

1996

High Radix Cordic Rotation based on Selection by Rounding [doi]
E. Antelo, J.D. Bruguera, T. Lang, J. Villalba, E.L. Zapata
2nd International European Conference on Parallel Processing (EuroPar'96), Lyon (France), August 1996
(Springer, LNCS 1124, L. Bouge, P. Fraigniaud, A. Mignotte and Y. Robert, Eds., pp. 155-164)

Radix-4 Vectoring CORDIC Algorithm and Architectures [doi]
J. Villalba, J.C. Arrabal, E.L. Zapata, E. Antelo, J.D. Bruguera
International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96), Chicago (IL, USA), August 1996

CORDIC Based Parallel/Pipelined Architecture for the Hough Transform [doi]
J.D. Bruguera, N. Guil, T. Lang, J. Villalba, E.L. Zapata
Journal of VLSI Signal Processing for Signal, Image and Video Technology, 12, June 1996, pp. 207-221

1995

A Fast Hough Transform for Segment Detection [doi]
N. Guil, J. Villalba, E.L. Zapata
IEEE Transactions on Image Processing, 4 (11), November 1995, pp. 1541-1548

Digit On-Line Large Radix CORDIC Rotator [doi]
R.R. Osorio, E. Antelo, J.D. Bruguera, J. Villalba, E.L. Zapata
International Conference on Application-Specific Array Processors (ASAP'95), Strasbourg (France), July 1995

CORDIC Architectures with Parallel Compensation of the Scale Factor [doi]
J. Villalba, J.A. Hidalgo, E.L. Zapata, E. Antelo, J.D. Bruguera
International Conference on Application-Specific Array Processors (ASAP'95), Strasbourg (France), July 1995

Redundant CORDIC Rotator Based on Parallel Prediction [doi]
E. Antelo, J.D. Bruguera, J. Villalba, E.L. Zapata
12th IEEE Symposium on Computer Arithmetic (Arith'95), Bath (UK), July 1995

1994

1993

1992

Transformada Rapida de Hough para la Deteccion de Segmentos
N. Guil, J. Villalba, E.L. Zapata
V Simposium Nacional de Reconocimiento de Formas y Analisis de Imagenes, Valencia (Spain), September 1992

All Papers Author: J. Villalba