All Papers
Author: J. Hormigo

2024

HUB Meets Posit: Arithmetic Units Implementation [doi]
R. Murillo, J. Hormigo, A.A. del Barrio, G. Botella
IEEE Transactions on Circuits and Systems II: Express Briefs, 71 (1), January 2024, pp. 440-444

2023

High-Throughput DTW Accelerator with Minimum Area in AMD FPGA by HLS [doi]
M. Hormigo-Jimenez, J. Hormigo
38th Conference on Design of Circuits and Integrated Systems (DCIS'23), Malaga (Spain), November 2023

Book Chapter: Aceleración del DTW en FPGA [doi]
M. Hormigo-Jimenez, J. Hormigo
Investigaciones DACIU 2022/2023
(Fundacion Avanza, pp. 407-412, April 2023)

2022

High-Radix Formats for Enhancing Floating-Point FPGA Implementations [doi]
J. Villalba, J. Hormigo
Circuits, Systems, and Signal Processing, 41, March 2022, pp. 1683-1703

2021

Introduce Metodologías Activas en tu Clase, Indispensable en Tiempos de Pandemia [link]
E. Hendrix, F.M. Castro, D.A. Constantinescu, F. Corbera, S. Gonzalez-Navarro, M. Gonzalez, J. Hormigo, J.R. Cozar, A. Rodriguez
XXXI Jornadas de Paralelismo (JP'20/21) (parte de las Jornadas Sarteco), Malaga (Spain), September 2021

FPGA Acceleration of Bit-True Simulations for Word-Length Optimization [doi]
J. Hormigo, G. Caffarena
IEEE 28th Symposium on Computer Arithmetic (ARITH'21), Lyngby, Denmark, June 2021

Efficient Floating-Point Givens Rotation Unit [doi]
J. Hormigo, S.D. Muñoz
Circuits, Systems, and Signal Processing, 40 (5), May 2021, pp. 2419-2442

2020

New Results on Non-normalized Floating-Point Formats [doi]
S. Gonzalez-Navarro, J. Hormigo
IEEE Transactions on Computers, 69 (12), December 2020, pp. 1733-1744

Floating-Point Fused Multiply-Add under HUB Format [doi]
J. Hormigo, J. Villalba, S. Gonzalez-Navarro
IEEE 27th Symposium on Computer Arithmetic (ARITH'20), Portland (OR, USA), June 2020

2019

Fast HUB Floating-Point Adder for FPGA [doi]
J. Villalba, J. Hormigo, S. Gonzalez-Navarro
IEEE Transactions on Circuits and Systems II: Express Briefs, 66 (6), June 2019, pp. 1028-1032

Reproducible Summation Under HUB Format [doi]
J. Villalba, J. Hormigo, F. Jaime
IEEE 26th Symposium on Computer Arithmetic (ARITH'19), Kyoto (Japan), June 2019

Designing a Project for Learning Industry 4.0 by Applying IoT to Urban Garden [doi]
J. Hormigo, A. Rodriguez
IEEE Revista Iberoamericana de Tecnologias del Aprendizaje, 14 (2), May 2019, pp. 58-65

2018

Unbiased Rounding for HUB Floating-Point Addition [doi]
J. Villalba, J. Hormigo, S. Gonzalez-Navarro
IEEE Transactions on Computers, 67 (9), September 2018, pp. 1359-1365

Project Based Learning on Industrial Informatics: Applying IoT to Urban Garden [doi]
J. Hormigo, A. Rodriguez
XIII Technologies Applied to Electronics Teaching Conference (TAEE'18), La Laguna (Spain), June 2018

2017

Introduction to the Special Issue on Computer Arithmetic [doi]
J. Hormigo, J. Muller, S. Oberman, N. Revol, A. Tisserand, J. Villalba
IEEE Transactions on Computers, 66 (12), December 2017, pp. 1991-1993

Floating Point Square Root under HUB Format [doi]
J. Villalba, J. Hormigo
IEEE International Conference on Computer Design (ICCD’2017), Boston (MA), USA, November 2017

Normalizing or Not Normalizing? An Open Question for Floating-Point Arithmetic in Embedded Systems [doi]
S. Gonzalez-Navarro, J. Hormigo
IEEE 24th Symposium on Computer Arithmetic (ARITH’17), London (UK), July 2017

HUB Floating Point for Improving FPGA Implementations of DSP Applications [doi]
J. Hormigo, J. Villalba
IEEE Transactions on Circuits and Systems II: Express Briefs, 64 (3), March 2017, pp. 319-323

2016

New Formats for Computing with Real-Numbers under Round-to-Nearest [doi]
J. Hormigo, J. Villalba
IEEE Transactions on Computers, 65 (7), July 2016, pp. 2158-2168

Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest [doi]
J. Hormigo, J. Villalba
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24 (6), June 2016, pp. 2369-2377

2015

High-Throughput FPGA Implementation of QR Decomposition [doi]
S.D. Muñoz, J. Hormigo
IEEE Transactions on Circuits and Systems II: Express Briefs, 62 (9), September 2015, pp. 861-865

Improving Fixed-Point Implementation of QR Decomposition by Rounding-to-Nearest [doi]
S.D. Muñoz, J. Hormigo
19th IEEE International Symposium on Consumer Electronics (ISCE’15), Madrid (Spain), June 2015

Simplified Floating-Point Units for High Dynamic Range Image and Video Systems [doi]
J. Hormigo, J. Villalba
19th IEEE International Symposium on Consumer Electronics (ISCE’15), Madrid (Spain), June 2015

2014

Optimizing DSP Circuits by a New Family of Arithmetic Operators [doi]
J. Hormigo, J. Villalba
48th Asilomar Conference on Signals, Systems and Computers, Pacific Grove (CA, USA), November 2014

2013

Multioperand Redundant Adders on FPGAs [doi]
J. Hormigo, J. Villalba, E.L. Zapata
IEEE Transactions on Computers, 62 (10), October 2013, pp. 2013-2025

Self-Reconfigurable Constant Multiplier for FPGA [doi]
J. Hormigo, G. Caffarena, J.P. Oliver, E. Boemo
ACM Transactions on Reconfigurable Technology and Systems, 6 (3), October 2013, pp. Art. No. 14

Efficient Floating-Point Representation for Balanced Codes for FPGA Devices [doi]
J. Villalba, J. Hormigo, F. Corbera, M. Gonzalez, E.L. Zapata
IEEE 31st International Conference on Computer Design (ICCD'13), Asheville (NC), USA, October 2013 (Best Paper Award)

2012

FGPA Implementation of QR Decomposition for Medium Size Matrices
S.D. Muñoz, J. Hormigo, E.L. Zapata
XXVII Conference on Design of Circuits and Integrated Systems (DCIS'12), Avignon (France), November 2012

A Study of Decimal Left Shifters for Binary Numbers [doi]
S. Gonzalez-Navarro, J. Hormigo, M.J. Schulte
Journal of Information and Computation, 216, July 2012, pp. 47-56

Acelerador Hardware de Bajo Coste para Bus PCI Convencional [link]
F. Quiles, M.A. Montijano, C.C. Moreno, M.Brox, M. Ortiz, J. Hormigo, J. Villalba
Annual Seminar on Automation, Industrial Electronics and Instrumentation (SAAEI’12), Guimaraes (Portugal), July 2012

Radix-2 Multioperand and Multiformat Streaming Online Addition [doi]
J. Villalba, T. Lang, J. Hormigo
IEEE Transactions on Computers, 61 (6), June 2012, pp. 790-803

2011

Convolution Computation in FPGA Based on Carry-Save Adders and Circular Buffers [doi]
C.D. Moreno, M.P. Martinez, F.J. Bellido, J. Hormigo, M.A. Ortiz, F.J. Quiles
3rd International ICST Conference on IT Revolutions (ICST’11), Cordoba (Spain), March 2011

High-Speed Algorithms and Architectures for Range Reduction Computation [doi]
F.J. Jaime, M.A. Sanchez, J. Hormigo, J. Villalba, E.L. Zapata
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19 (3), March 2011, pp. 512-516

2010

UCORE: Reconfigurable Platform for Educational Purposes [doi]
F. Quiles, M. Ortiz, J. Hormigo, J. Villalba
International Conference on ReConFigurable Computing and FPGAs, Cancun (Mexico), December 2010

Enhanced Scaling-Free CORDIC [doi]
F.J. Jaime, M.A. Sanchez, J. Hormigo, J. Villalba, E.L. Zapata
IEEE Transactions on Circuits and Systems I, 57 (7), July 2010, pp. 1654-1662

2009

Efficient Mapping on FPGA of Convolution Computation Based on Combined CSA-CPA Accumulator [doi]
C.D. Moreno, F. Quiles, M. Ortiz, M. Brox, J. Hormigo, J. Villalba, E.L. Zapata
16th IEEE International Conference on Electronics, Circuits and Systems (ICECS'09), Yasmine Hammamet, Tunisia, December 2009

Efficient Implementation of Carry-Save Adders in FPGAs [doi]
J. Hormigo, M. Ortiz, F. Quiles, F.J. Jaime, J. Villalba, E.L. Zapata
20th IEEE International Conference on Applicaction Specific Systems, Architectures and Processors (ASAP'09), Boston (MA), USA, July 2009

2008

Pipelined Architecture for Additive Range Reduction [doi]
F.J. Jaime, J. Villalba, J. Hormigo, E.L. Zapata
Journal of Signal Processing Systems, 53 (1-2), November 2008, pp. 103-112

New SIMD Instructions set for Image Processing Applications Enhacement [doi]
F.J. Jaime, J. Hormigo, J. Villalba, E.L. Zapata
15th IEEE International Conference on Image Processing (ICIP'08), San Diego (CA), USA, October 2008

SIMD Enhacements for a Hough Transform Implementation [doi]
F.J. Jaime, J. Hormigo, J. Villalba, E.L. Zapata
11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD'08), Parma (Italy), September 2008

Decimal Left Shifters for Binary Numbers
J. Hormigo, S. Gonzalez-Navarro, M. Schulte
8th Conference on Real Numbers and Computers (RNC8), Santiago de Compostela, Spain, July 2008

2007

Profit Analysis of Instructions with Parallel Access to Memory
F.J. Jaime, J. Villalba, J. Hormigo, E.L. Zapata
Workshop on Application Specific Processors (WASP 2007), Salzburg, Austria, October 2007

Improving the Troughput of On-line Addition for Data Streams [doi]
J. Villalba, J. Hormigo, T. Lang
18th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP’07), Montreal, Canada, July 2007

Hardware Accelerators for the Microblaze Software Embedded Processor [link]
M. Hernandez-Calviño, J.I. Benavides, S.R. Geninatti, J. Hormigo, J. Villalba
III Southern Conference on Programmable Logic (SPL2007), Mar del Plata, Argentina, February 2007 (poster)

2006

Pipelined Range Reduction for Floating Point Numbers [doi]
F.J. Jaime, J. Villalba, J. Hormigo, E.L. Zapata
17th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'06), Steamboat Springs (CO, USA), September 2006

Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA [doi]
J. Olivares, J.I. Benavides, J. Hormigo, J. Villalba, E.L. Zapata
16th International Conference on Field Programmable Logic and Applications (FPL'06), Madrid (Spain), August 2006

SAD Computation based on On-line Arithmetic for Motion Estimation [doi]
J. Olivares, J. Hormigo, J. Villalba, J.I. Benavides, E.L. Zapata
Microprocessors and Microsystems, 30 (5), August 2006, pp. 250-258

Pipelined Architecture for Accurate Floating Point Range Reduction [link]
F.J. Jaime, J. Villalba, J. Hormigo, E.L. Zapata
7th Conference on Real Numbers and Computers (RNC'06), Loria (Nancy, France), July 2006

2005

Hardware para Intervalos
J. Hormigo, E.L. Zapata, J. Villalba
El Análisis de Intervalos en España: Desarrollos, Herramientas y Aplicaciones, Documenta Universitaria, 2005, pp. 87-95

On-line Multioperand Addition Based on On-line Full-Adders [doi]
J. Villalba, J. Hormigo, J.M. Prades, E.L. Zapata
16th IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP’05), Samos (Greece), July 2005

Hardware Implementation of the Wavelet Transform for JPEG2000 [doi]
J. Hormigo, J.M. Prades, J. Villalba, E.L. Zapata
SPIE Symposium on Microtechnologies for the New Millennium, Sevilla (Spain), May 2005
(Proc. SPIE 5837, VLSI Circuits and Systems II, J.F. Lopez, F.V. Fernandez, J.M. Lopez-Villegas and J.M. dela Rosa, Eds.)

2004

Image Segmentation Using the Wigner-Ville Distribution [doi]
J. Hormigo, G. Cristobal
Advances in Imaging and Electron Physics, Vol. 131, Ed. Elsevier, 2004, pp. 65-80

Estimación de Movimiento en MPEG mediante Técnicas de Aritmética On-Line sobre FPGA [link]
J. Olivares, J. Hormigo, J.I. Benavides, J. Villalba, E.L. Zapata
Revista Iberoamericana de Sistemas, Cibernética e Informática, 1 (2), 2004, pp. 36-41

Optimized FPGA Implementation of Trigonometric Functions with Large Input Arguments
J. Hormigo, M. Sanchez, M. Gonzalez, G. Bandera, J. Villalba
XIX Conference on Design of Circuits and Integrated Systems (DCIS'04), Bordeaux (France), November 2004

Alternativas al Cálculo de la Estimación de Movimiento en MPEG
J.I. Benavides, J. Hormigo, J. Olivares, J. Villalba
XV Jornadas de Paralelismo (JJPP'04), Almeria (Spain), September 2004

Minimum Sum of Absolute Differences Implementation in a Single FPGA Device [doi]
J. Olivares, J. Hormigo, J. Villalba, I. Benavides
14th International Conference on Field Programmable Logic and Applications (FPL'04),, Leuven (Belgium), August-September 2004
(Springer, LNCS 3203, J. Becker, M. Platzner and S. Vernalde, Eds., pp. 986-990)

Estimación de Movimiento en MPEG Mediante Técnicas de Aritmética On-Line Sobre FPGA
J. Hormigo, J. Olivares, I. Benavides, J. Villalba
3ra Conferencia Iberoamericana en sistemas, Cibernética e Informática (CISCI'04), Orlando (FL, USA), July 2004

New On-Line Comparator with No On-Line Delay
J. Hormigo, J. Olivares, J. Villalba, I. Benavides
8th World Muticonference on Systemics, Cybernetics and Informatics (SCI2004), Orlando (FL, USA), July 2004

CORDIC Processor for Variable-Precision Interval Arithmetic [doi]
J. Hormigo, J. Villalba, E.L. Zapata
Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 37 (1), May 2004, pp. 21-39

Evaluation of Elementary Functions Using Multimedia Features [doi]
G. Bandera, M. Gonzalez, J. Villaba, J. Hormigo, E.L. Zapata
18th International Parallel and Distributed Processing Symposium (IPDPS'04), Santa Fe (NM, USA), April 2004

2003

Implementación de un Sumador Matricial en FPGA Mediante Técnicas de Aritmrética On-Line Radix-2 SD
J. Olivares, J.I. Benavides, J. Villalba, J. Hormigo
XIV Jornadas de Paralelismo (JJPP'03), Leganes, Madrid (Spain), September 2003

Texture Segmentation and a Analysis Using Local Spectral Methods [doi]
G. Cristobal, S. Fischer, M. Forero-Vargas, R. Redondo, J. Hormigo
7th International Symposium on Signal Processing and its Applications (ISSPA'03), Paris (France), July 2003

2002

Polynomial Evaluation on Multimedia Processor [doi]
J. Villalba, G. Bandera, M. Gonzalez, J. Hormigo, E.L. Zapata
13th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'02), San Jose (CA, USA), July 2002, pp. 265-277

2001

Bit Stream Processor for Object Based MPEG-4 Profiles [doi]
K.A. Jacob, J. Hormigo
35th Asilomar Conference on Signals, Systems and Computers, Pacific Grove (CA, USA), November 2001

Variable-Precision Exponential Evaluation [doi]
J. Hormigo, J. Villalba, M.J. Schulte
Scientific Computing, Validated Numerics, Interval Methods
(Springer, W. Kraemer and J.W. von Gudenberg, Eds., pp. 19-28, 2001)

2000

MMX-like Architecture Extension to Support the Rotation Operation [doi]
J. Villalba, J. Hormigo, M. Gonzalez, E.L. Zapata
IEEE International Conference on Multimedia and Expo (ICME'00), New York (NY, USA), July-August 2000

1999

FPGA Implementation of a CORDIC Processor with Reduced Number of Iterations
M. Gonzalez, J. Hormigo, J. Villalba, E. Saez, E.L. Zapata
14th Conference on Design of Circuits and Integrated Systems (DCIS'99), Palma de Mallorca (Spain), November 1999

Arithmetic Unit for the Computation of Interval Elementary Functions [doi]
J. Hormigo, J. Villalba, E.L. Zapata
25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millenium, Milan (Italy), September 1999

Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm [doi]
J. Hormigo, J. Villalba, E.L. Zapata
14th IEEE Symposium on Computer Arithmetic (ARITH-14), Adelaide (Australia), April 1999

Texture Segmentation Through Eigen-Analysis of the Pseudo-Wigner Distribution [doi]
G. Cristobal, J. Hormigo
Pattern Recognition Letters, 20 (3), March 1999, pp. 337-345

Book Chapter: A Hardware Approach to Interval Artihmetic for Sine and Cosine Functions [doi]
J. Hormigo, J. Villalba, E.L. Zapata
Developments in Reliable Computing, (Springer, Dordrecht, T. Csendes Ed., pp. 31-41, 1999)

1998

FPGA Implementation of a Variable Precision CORDIC Processor
E. Saez, J. Villalba, J. Hormigo, F.J. Quiles, J.I. Benavides, E.L. Zapata
13th Conference on Design of Circuits and Integrated Systems (DCIS'98), Madrid (Spain), November 1998

CORDIC Algorithm with Digits Skipping [doi]
J. Hormigo, J. Villalba, E.L. Zapata
32th Asilomar Conference on Signals, Systems and Computers, Pacific Grove (CA, USA), November 1998

A Hardware Approximation to Interval Arithmetic for Sine and Cosine Functions [doi]
J. Hormigo, J. Villalba, E.L. Zapata
IMACS/GAMS International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics (SCAN'98), Szeged (Hungary), September 1998
(Springer, Developments on Reliable Computing, T. Csendes, Ed., pp. 31-41)

High Resolution Spectral Analysis of Images Using the Pseudo-Wigner Distribution [doi]
J. Hormigo, G. Cristobal
IEEE Transactions on Signal Processing, 46 (6), June 1998, pp. 1757-1763

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