All papers: Last 5 Years
Author: J. Villalba

2024

Floating Point HUB Adder for RISC-V Sargantana Processor [arXiv]
G. Bandera, J. Salamero, M. Moreto, J. Villalba
arXiv:2401.09464v1 [cs.AR], January 2024

2023

2022

High-Radix Formats for Enhancing Floating-Point FPGA Implementations [doi]
J. Villalba, J. Hormigo
Circuits, Systems, and Signal Processing, 41, March 2022, pp. 1683-1703

2021

2020

Floating-Point Fused Multiply-Add under HUB Format [doi]
J. Hormigo, J. Villalba, S. Gonzalez-Navarro
IEEE 27th Symposium on Computer Arithmetic (ARITH'20), Portland (OR, USA), June 2020