All papers: Last 5 Years
Author: J. Hormigo

2024

HUB Meets Posit: Arithmetic Units Implementation [doi]
R. Murillo, J. Hormigo, A.A. del Barrio, G. Botella
IEEE Transactions on Circuits and Systems II: Express Briefs, 71 (1), January 2024, pp. 440-444

2023

High-Throughput DTW Accelerator with Minimum Area in AMD FPGA by HLS [doi]
M. Hormigo-Jimenez, J. Hormigo
38th Conference on Design of Circuits and Integrated Systems (DCIS'23), Malaga (Spain), November 2023

Book Chapter: Aceleración del DTW en FPGA [doi]
M. Hormigo-Jimenez, J. Hormigo
Investigaciones DACIU 2022/2023
(Fundacion Avanza, pp. 407-412, April 2023)

2022

High-Radix Formats for Enhancing Floating-Point FPGA Implementations [doi]
J. Villalba, J. Hormigo
Circuits, Systems, and Signal Processing, 41, March 2022, pp. 1683-1703

2021

Introduce Metodologías Activas en tu Clase, Indispensable en Tiempos de Pandemia [link]
E. Hendrix, F.M. Castro, D.A. Constantinescu, F. Corbera, S. Gonzalez-Navarro, M. Gonzalez, J. Hormigo, J.R. Cozar, A. Rodriguez
XXXI Jornadas de Paralelismo (JP'20/21) (parte de las Jornadas Sarteco), Malaga (Spain), September 2021

FPGA Acceleration of Bit-True Simulations for Word-Length Optimization [doi]
J. Hormigo, G. Caffarena
IEEE 28th Symposium on Computer Arithmetic (ARITH'21), Lyngby, Denmark, June 2021

Efficient Floating-Point Givens Rotation Unit [doi]
J. Hormigo, S.D. Muñoz
Circuits, Systems, and Signal Processing, 40 (5), May 2021, pp. 2419-2442

2020

New Results on Non-normalized Floating-Point Formats [doi]
S. Gonzalez-Navarro, J. Hormigo
IEEE Transactions on Computers, 69 (12), December 2020, pp. 1733-1744

Floating-Point Fused Multiply-Add under HUB Format [doi]
J. Hormigo, J. Villalba, S. Gonzalez-Navarro
IEEE 27th Symposium on Computer Arithmetic (ARITH'20), Portland (OR, USA), June 2020